The invention is in the field of logic circuitry, and particularly concerns multiple input CMOS logic circuits.
In CMOS design, multiple input logic circuits are conventionally assembled by cascading basic logic circuits with few inputs. For example, in FIG. 1, a prior art AND gate with 32 inputs is implemented using eleven 4-input AND gates. Conventional CMOS logic circuits are limited to a small number of inputs, typically, 5 or less. More can be added only at the expense of delay of circuit response to a change in input. As a consequence, the total transistor count and actual area occupied by a multiple input CMOS circuit increase almost geometrically with the number of inputs required.
The requirement to use multiple circuit elements with few inputs for implementing CMOS logic results in a technical limit in the design and fabrication of very large scale integrated circuitry (VLSIC). It should be evident that CMOS circuit density would be improved substantially if multiple input CMOS logic could be constructed from a single fundamental configuration. For example, a multiple input CMOS circuit which implemented the 32 input AND gate of FIG. 1 in a single fundamental circuit element would result in the AND gate of FIG. 2. Obviously, the AND gate of FIG. 2 would provide a substantial increase in circuit density over that of FIG. 1 by reducing the sets of switching and interface circuitry required for the basic element from 11 to 1.